1. Field
The present disclosure pertains to the field of processors. More particularly, the present disclosure pertains to a processor that may alter, transform, mutate, or otherwise “morph” instructions when difficulties are encountered during one or more initial attempts to execute such instructions.
2. Description of Related Art
Improving the performance of computers or other processing systems generally improves overall throughput and/or provides a better user experience. Such improved system performance may be achieved by increasing the rate at which instructions for the system are processed by a processor. Accordingly, it is desirable to produce advanced processors with improved instruction throughput.
Continuing to increase the performance of a processor, however, is a difficult task. Prior art processors already employ techniques of branch prediction, speculative execution, and out-of-order (OOO) execution. Additionally, such processors typically include multiple parallel execution units to process numerous instructions in parallel. As increasing amounts of parallel hardware are employed, providing sufficient instructions to keep this hardware busy becomes increasingly difficult due to limited instruction level parallelism which may be extracted or due to instruction dependencies present in many existing software programs.
Multi-threading is one technique that may be used to reduce idle time for parallel execution units. Multi-threading allows multiple programs or threads to share hardware resources. Due to the separate program sequences being executed, there is less likelihood of instruction dependencies seriously reducing execution unit utilization. Such multi-threaded machines inherently benefit from the additional parallelism resulting from executing multiple threads as long as multiple threads can be extracted or are explicitly provided by the software being executed.
Thus, large amounts of effort in designing modern processors have been applied to such instruction-dispatch focused techniques. These techniques at least in part strive to increase the number of instructions dispatched to the intended execution units. At times, however, significant latency-causing problems are encountered post-dispatch (e.g., faults, numeric computation problems, cache misses, etc.). An execution unit in a prior art processor is generally “stuck” with the instruction it got once the instruction has been dispatched to the execution unit.
Instruction decoding is a type of an alteration of an instruction that occurs after an instruction is received by a processor. Instruction decoding, however, generally involves expanding an instruction into microinstructions, or changing the encoding of an instruction into a more convenient form or another instruction set for execution by an execution unit. Instruction decoding does not generally go beyond a particular mapping of an input instruction to either individual signals or individual microinstructions. Moreover, instruction decoding is an inherently front-end operation in processing systems and lacks the ability to incorporate information gleaned throughout execution of an instruction.
Thus, prior art processors generally do not morph original instructions into altered instructions that execute more efficiently or otherwise differently than the original instructions once attempted execution has occurred.